The present invention relates generally to leadless leadframe semiconductor packages. More specifically, the invention relates to pin indicators for identifying a selected contact pad or region in such packages.
A leadless leadframe package (LLP) is a relatively new integrated circuit package design that contemplates the use of a conductive (typically copper) leadframe type substrate structure in the formation of a chip scale package (CSP). As illustrated in FIGS. 1A-1C, in typical leadless leadframe packages, a copper leadframe strip or panel 101 is patterned (typically by stamping or etching) to define a plurality of device area arrays 103 of chip substrate features. Each chip substrate feature includes a die attach pad 107 and a plurality of contacts 109 disposed about their associated die attach pad 107. Very fine tie bars 111 are used to support the die attach pads 107 and contacts 109.
During assembly, dice are attached to the respective die attach pads and conventional wire bonding is used to electrically couple bond pads on each die to their associated contacts 109 on the leadframe strip 101. After the wire bonding, a plastic cap is molded over the top surface of each array 103 of wire bonded dice. The dice are then singulated and tested using conventional sawing and testing techniques.
FIG. 1D illustrates cross-sectional view of a typical resulting leadless leadframe package. The die attach pad 107 supports a die 120 which is electrically connected to its associated contacts 109 by bonding wires 122. A plastic cap 125 encapsulates the die 120 and bonding wires 122 and fills the gaps between the die attach pad 107 and the contacts 109 thereby serving to hold the contacts in place. It should be appreciated that during singulation, the tie bars 111 are cut and therefore the only materials holding the contacts 109 in place is the molding material. The resulting packaged chip can then be surface mounted on a printed circuit board or other substrate using conventional techniques.
Although leadless leadframe packaging has proven to be a cost effective packaging arrangement, there are continuing efforts to further reduce the costs associated with packaging. One persistent issue in packaging generally is the need and desire to provide an indication of the chip""s orientation directly on the package. This insures that a device can readily be properly oriented when it is mounted on a printed circuit board (or other substrate). One common mechanism for doing this is to provide a visual identifying mark near a particular one of the pins (typically pin 1).
Various methods have been used to identify pin 1 on LLP""s and other packages. Some methods use ink or lasers to create a mark on the molding material near pin 1. These methods are undesirable because ink applicating machines and lasers are required. To avoid the need for additional machines, markers have been formed directly on the leadframes during the chemical etching process that is used to form the leadless leadframes. For example, a protrusion along the edge of a die attach pad at a point adjacent to pin 1 may serve as a marker. Alternatively, a protrusion, i.e. stem, may be formed next to pin 1 such that it is exposed on the perimeter with the contact that surrounds the die attach pad. Unfortunately, the position of these protrusions occupies extra space in the semiconductor device and therefore effectively increases the required size of the devices. In the case of a protrusion on the edge of the die attach pad, a larger spacing is required between the die attach pad and the contacts.
In view of the foregoing, it would be advantageous to be able to provide a simple, low cost mechanism for providing pin identifying marks in leadless leadframe packages.
The present invention is generally directed at leadframe based packages, such as leadless leadframe packages, that include an orientation indicator that is integrally formed with the leadframe. In one aspect, a leadless leadframe package is described in which the leadframe includes a die attach pad, a plurality of contact fingers, a tie bar extending from the die attach pad, and an indicator stem extending from the tie bar. An integrated circuit die is mounted on the die attach pad and appropriate connectors (such as bonding wires) electrically couple bond pads on the die to associated contact fingers. A protective cap (typically formed from a plastic material) encapsulates the connectors and covers at least a portion of the die and contact fingers while leaving at least a portion of a bottom surface area of the contact fingers exposed to form external electrical contacts for the package. The protective cap leaves an identifying end of the indicator stem exposed through the surface of the protective cap to facilitate identification of a particular contact or region of the package.
In some embodiments, the indicator stem extends perpendicularly upward from the tie bar such that the combined thickness of the indicator stem and the tie bar is substantially the same thickness as the thickness of the contact fingers. In other embodiments, the indicator stem extends to the side of the tie bar and is substantially the same thickness as the contact fingers. The indicator stem may have a wide variety of geometries.
In another aspect of the invention, a leadless leadframe panel for use in semiconductor packaging is described. The leadless leadframe panel is formed from a conductive sheet of material and has a two dimensional array of device areas defined thereon. Each device area includes a die attach pad, a plurality of contact fingers, a tie bar extending from the die attach pad and an indicator stem extending from the tie bar. The indicator stem has a thickness or height that permits an identifying end thereof to be substantially coplaner with an exposed surface of the contact fingers that the tie bar is not co-planer with. As suggested above, the device areas (which become the leadless leadframes in packaged devices) may have a wide variety of layouts and geometries.
In a method aspect of an invention, a method of producing the described leadless leadframe having integral indicator pins is described. An appropriate substrate panel that includes an array of device areas each having a die attach pad, contact fingers and at least one tie bar attached to the die attach pad is described. The tie bars are partially etched to reduce their heights, while leaving a portion (typically a relatively small portion) of at least some of the tie bars unetched to form the indicator stems. The indicator stems may then be used to identify a selected region or contact finger of the associated device area. The described panels may then be used to package an array of semiconductor devices.